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PIC18F4550 - PIC with Universal Serial Bus Interface Pinout Universal Serial Bus Features:
USB V2.0 Compliant
Low Speed (1.5 Mb/s) and Full Speed (12 Mb/s)
Supports Control, Interrupt, Isochronous and Bulk
Transfers
Supports up to 32 Endpoints (16 bidirectional)
1-Kbyte Dual Access RAM for USB
On-Chip USB Transceiver with On-Chip Voltage
Regulator
Interface for Off-Chip USB Transceiver
Streaming Parallel Port (SPP) for USB streaming
transfers (40/44-pin devices only)
Power-Managed Modes:
Run: CPU on, peripherals on
Idle: CPU off, peripherals on
Sleep: CPU off, peripherals off
Idle mode currents down to 5.8 ΅A typical
Sleep mode currents down to 0.1 ΅A typical
Timer1 Oscillator: 1.1 ΅A typical, 32 kHz, 2V
Watchdog Timer: 2.1 ΅A typical
Two-Speed Oscillator Start-up
Flexible Oscillator Structure:
Four Crystal modes, including High Precision PLL
for USB
Two External Clock modes, up to 48 MHz
Internal Oscillator Block:
- 8 user-selectable frequencies, from 31 kHz
to 8 MHz
- User-tunable to compensate for frequency drift
Secondary Oscillator using Timer1 @ 32 kHz
Dual Oscillator options allow microcontroller and
USB module to run at different clock speeds
Fail-Safe Clock Monitor:
- Allows for safe shutdown if any clock stops
Peripheral Highlights:
High-Current Sink/Source: 25 mA/25 mA
Three External Interrupts
Four Timer modules (Timer0 to Timer3)
Up to 2 Capture/Compare/PWM (CCP) modules:
- Capture is 16-bit, max. resolution 5.2 ns (TCY/16)
- Compare is 16-bit, max. resolution 83.3 ns (TCY)
- PWM output: PWM resolution is 1 to 10-bit
Enhanced Capture/Compare/PWM (ECCP) module:
- Multiple output modes
- Selectable polarity
- Programmable dead time
- Auto-shutdown and auto-restart
Enhanced USART module:
- LIN bus support
Master Synchronous Serial Port (MSSP) module
supporting 3-wire SPI (all 4 modes) and I2C
Master and Slave modes
10-bit, up to 13-channel Analog-to-Digital Converter
module (A/D) with Programmable Acquisition Time
Dual Analog Comparators with Input Multiplexing
Special Microcontroller Features:
C Compiler Optimized Architecture with optional
Extended Instruction Set
100,000 Erase/Write Cycle Enhanced Flash
Program Memory typical
1,000,000 Erase/Write Cycle Data EEPROM
Memory typical
Flash/Data EEPROM Retention: > 40 years
Self-Programmable under Software Control
Priority Levels for Interrupts
8 x 8 Single-Cycle Hardware Multiplier
Extended Watchdog Timer (WDT):
- Programmable period from 41 ms to 131s
Programmable Code Protection
Single-Supply 5V In-Circuit Serial
Programming (ICSP) via two pins
In-Circuit Debug (ICD) via two pins
Optional dedicated ICD/ICSP port (44-pin devices only)
Wide Operating Voltage Range (2.0V to 5.5V)
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